The invention relates to electronic semiconductor devices, and, more particularly, to dielectric structures and fabrication methods for such structures.
The performance of high density integrated circuits is dominated by metal interconnect level RC time delays due to the resistivity of the metal lines and the capacitive coupling between adjacent lines. The capacitive coupling can be reduced by decreasing the relative permittivity (dielectric constant, k) of the dielectric (electrical insulator) between adjacent lines.
Various dielectric materials have been suggested for use in silicon integrated circuits to replace the commonly used silicon dioxide (k about 4.0). The leading candidates are fluorinated silicon dioxide (k about 3.0-4.0), organic polymers such as polyimide, parylene, amorphous teflon (k about 1.9-3.9), and porous dielectrics such as silicon dioxide xerogels (k dependent upon pore size and typically 1.3-3.0).
Similarly, decreasing the resistivity of the interconnect metal by substituting copper (or silver) for the commonly used aluminum and tungsten will also reduce the RC time constant.
However, copper interconnects typically require an inlaid (damascene) process for fabrication which uses chemical mechanical polishing (CMP), and CMP can easily damage the mechanically fragile xerogel. In addition, standard post-CMP cleanup techniques, such as those involving buff processing, megasonic chemical baths, high pressure sprays, and brush scrubbing of wafer surfaces have been ineffective in cleaning xerogel material. In particular, in the fabrication of integrated circuits involving copper inlaid processes, when the copper is polished from the surface of the xerogel, the xerogel has shown susceptibility to being damaged. Further, copper compounds in CMP slurries can diffuse into the xerogel, and removal of the copper compounds cannot be accomplished without damage to the xerogel.
Thus the current xerogel with copper interconnects using CMP processing have manufacturing problems.
The present invention provides silicon carbide layers as polish and etch stops on a dielectric with the silicon carbide also acting as a protection layer during cleanup and as a diffusion barrier during and after polishing. Preferred embodiments include an adhesion layer between the dielectric and the silicon carbide. The silicon carbide can remain as part of the final interconnect structure or be removed.
This has the advantage of robust CMP processing, including polishing metal damascene structures imbedded in relatively fragile dielectrics such as xerogels, parylenes, amorphous teflon, and other amorphous polymers, and additionally with other low-k dielectrics such as high density plasma fluorinated silicon dioxide and benzocyclobutenes. Of course, non-low-k dielectrics such as plasma enhanced tetraethoxysilane (PETEOS) oxides, siloxanes, and undoped high density plasma oxides may also be used. A further advantage is that the SiC etch and polish stop layers will have a lower dielectric constant (4.5-6) than the conventionally used Si3N4 (8).